/*
 * =====================================================================================
 * Copyright (C) 2023 Ingenic Semiconductor Co.,Ltd
 * All Rights Reserved
 *
 * Filename     : interrupt.h
 * Author       : Keven <keven.ywhan@ingenic.com>
 * Created      : 2024/06/19 11:47
 * Description  :
 *
 * =====================================================================================
 */

#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__

#define IRQ_CPU_BASE         (0)
#define IRQ_RISCV_SOFT       (IRQ_CPU_BASE + 3)
#define IRQ_RISCV_OST        (IRQ_CPU_BASE + 7)
#define IRQ_RISCV_INTC       (IRQ_CPU_BASE + 11)
#define IRQ_RISCV_MAILBOX    (IRQ_CPU_BASE + 16)

#define IRQ_INTC_BASE        (IRQ_CPU_BASE + 32)
#define IRQ_INTC0_PDMA       (IRQ_INTC_BASE + 10)
#define IRQ_INTC0_GPIO2      (IRQ_INTC_BASE + 15)
#define IRQ_INTC0_GPIO1      (IRQ_INTC_BASE + 16)
#define IRQ_INTC0_GPIO0      (IRQ_INTC_BASE + 17)
#define IRQ_INTC0_ISP        (IRQ_INTC_BASE + 29)
#define IRQ_INTC0_VIC        (IRQ_INTC_BASE + 30)

#define IRQ_INTC1_BASE       (IRQ_INTC_BASE + 32)
#define IRQ_INTC1_UART2      (IRQ_INTC1_BASE + 17)
#define IRQ_INTC1_UART1      (IRQ_INTC1_BASE + 18)
#define IRQ_INTC1_UART0      (IRQ_INTC1_BASE + 19)
#define IRQ_INTC1_I2C2       (IRQ_INTC1_BASE + 16)
#define IRQ_INTC1_IVDC       (IRQ_INTC1_BASE + 25)
#define IRQ_INTC1_I2C1       (IRQ_INTC1_BASE + 27)
#define IRQ_INTC1_I2C0       (IRQ_INTC1_BASE + 28)
#define IRQ_INTC1_RADIX      (IRQ_INTC1_BASE + 30)
#define IRQ_INTC1_HELIX      (IRQ_INTC1_BASE + 31)

#define IRQ_INTC_END         (IRQ_INTC_BASE + 64)
#define MAX_IRQ_NUM          IRQ_INTC_END

#define PLIC_CONFIG          (INTC_BASE + 0x0000)
#define PLIC_PRIORITYn       (INTC_BASE + 0x0004)
#define PLIC_PENDING_L       (INTC_BASE + 0x1000)
#define PLIC_PENDING_H       (INTC_BASE + 0x1004)
#define PLIC_ENABLE_L        (INTC_BASE + 0x2000)
#define PLIC_ENABLE_H        (INTC_BASE + 0x2004)
#define PLIC_THRESHOLDn      (INTC_BASE + 0x200000)
#define PLIC_CLAIMn          (INTC_BASE + 0x200004)

typedef enum IRQ_PRIORITY {
	IRQ_PRIORITY_LOW = 0,
	IRQ_PRIORITY_MIDDLE,
	IRQ_PRIORITY_HIGH,
	IRQ_PRIORITY_HIGHEST
} irq_priority_t;

typedef void (*irq_handler_t)(int32_t irq, void *data);

void request_irq(int32_t irq, irq_handler_t handler, void *data);
void enable_irq(int32_t irq);
void disable_irq(int32_t irq);
void release_irq(int32_t irq);

/* MASK CPU Intc. */
void enable_irq_cpu(int32_t irq);
void disable_irq_cpu(int32_t irq);

void handle_irq(int32_t irq);
void set_irq_priority(int32_t irq, irq_priority_t priority);

void ost_handler(int32_t irq, void *data);
void soft_handler(int32_t irq, void *data);
void mailbox_handler(int32_t irq, void *data);


#endif /* __INTERRUPT_H__ */
